1. Field of the Invention
The present invention relates to a program control device and a program control method. More particularly, the present invention relates to a program control device for managing cache information and performing program control. The invention also pertains to a method of manufacturing the device.
2. Description of the Related Art
It has been said that even if a processing speed of a CPU (Central Processing Unit) is increased, since the time for preparing data used in calculations or for writing calculation results in external memories becomes a bottleneck, improvement in the processing speed of the whole system is difficult.
Therefore, a cache as a high-speed memory with a small capacity is nowadays disposed between an external memory and a CPU. Thereby, a difference between a processing speed of the CPU and a cost for an access to the external memory can be absorbed, which can contribute to the improvement of the processing speed of the whole system.
However, since the cache is a high-speed memory but has a small capacity, only a small portion of data in the external memory can be stored in the cache.
More specifically, in the case where the CPU fetches data from the cache, when desired data is stored in the cache (cache hit), the data can be directly fetched from the cache.
However, when the desired data is not stored in the cache (cache miss), the data stored in the external memory must be fetched to the cache.
This cache miss causes a bottleneck in improvement of the processing speed of the whole system.
Therefore, for a method for reducing the cache misses and effectively using the cache, for example, the following method is proposed.
FIG. 16 is a flowchart showing a procedure for a conventional program control.
The conventional program control is performed by causing a computer to execute the procedure for the conventional program control shown in FIG. 16. That is, the computer executes the procedure for the program control to function as the conventional program control device.
By the conventional program control device, the following process is performed according to a flowchart shown in FIG. 16.
[Step S1] A project is created and a source program is compiled.
[Step S2] A measure range is set in the source program, if desired.
[Step S3] The source program is converted into a target program by a build process such as compile, assemble or link.
[Step S4] The target program is loaded into a main memory.
[Step S8] When the target program is loaded into the main memory, measurement of cache performance information (a cache hit rate and a cache miss rate) of the target program is executed by a CPU.
[Step S9] The cache performance information is obtained.
[Step S11] The cache performance information is displayed in GUI (Graphical User Interface).
[Step S13] From the displayed cache performance information, it is determined whether the program has sufficient performance. When the program has not sufficient performance, the process goes to step S14.
[Step S14] With reference to the cache performance information obtained in step S9, control is performed such as a change of logic in the program, a structure based on locality of external accesses, preposition to the cache and build options for a compiler.
After the control, the process returns to step S3 and passes through steps S3 to S11 again. In step S13, it is determined whether the program has sufficient performance. If the program has sufficient performance, the process goes to step S15.
[Step S15] A program having sufficient performance is obtained. Judging from the cache performance information, the process returns to step S1 or S3 according to user's need and remeasurement is performed.
Thus, there is proposed a method of displaying the cache hit rate and the cache miss rate by the above-described procedure to thereby generate an optimum linker option to reduce the cache misses.
In addition to the above procedure, there is also proposed a cache information display system (see, e.g., Japanese Unexamined Patent Application Publication No. 8-241208) having a storage function for storing, as internal information, cache information such as the capacity, the number of ways and the line size of the cache; an analysis function for recognizing a loop from the source program and analyzing the access conditions to the data in the loop; and a display function for displaying analysis results of the analysis function.
By the program control and cache information display system described above, information on the cache is displayed. Using this displayed information, a user personally changes a source or provides a compiler with user's known information to perform the program control. As a result, the cache misses can be reduced so that the cache can be effectively used.
However, in performing the above-described conventional program control to reduce the cache misses, the following problem occurs.
In the case of performing the control of the program such as a C language program to reduce the cache misses, the logic and allocation in the cache memory of specific functions from the cache misses must be optimized. In the conventional program control method, however, the cache miss rate is displayed but effects on other functions or variables sharing the same cache line are not found. Therefore, even if a cache conflict occurs between functions or variables, it is difficult to specify the causal function or variable.